In recent years, nonvolatile semiconductor storage devices such as a flash memory for storing information according to an amount of accumulated charges are widely known. Recently, a capacity of a NAND flash memory is increased. A personal computer incorporating the NAND flash memory as a secondary storage device is put to practical use.
The NAND flash memory is a semiconductor memory in which erase processing is necessary before writing data. The durable life of the NAND flash memory depends upon the number of times of erasing (the number of times of rewriting). Data erasing and data writing for the NAND flash memory are performed by applying high voltage between a substrate and a control gate to inject electrons into and discharge electrons from a floating gate. Therefore, when erase processing and write processing are performed a large number of times, a gate oxide film around the floating gate is deteriorated and the electrons injected into the floating gate are lost. It is likely that recorded data is broken.
Data recorded by a computer such as a personal computer has temporal locality and regional locality (see, for example, Non-Patent Document 1). Because of this characteristic, if data is directly recorded according to an address designated from the outside, rewrite processing and erase processing are concentrated in a specific area and respective storage devices are unequally deteriorated. Therefore, in the NAND flash memory of this type, processing called wear leveling for equally distributing data update sections in a semiconductor storage device is performed to generally equalize the number of times of erasing in all memory cells in the semiconductor storage device.
Further, in the NAND flash memory, a phenomenon called read disturb in which data in a read-out page and data in another page in the same block as the read-out page are unstable. The read disturb is a phenomenon in which, during data readout, because of word line potential (unselected word line potential) applied to a control gate of an unselected cell, for example, electrons are injected into a floating gate of a cell having a value “1” and the value of the cell is changed to “0”.
On the other hand, it is said that unlikelihood of the read disturb, i.e., durability against the read disturb is deteriorated as erasing and writing of data are repeated a larger number of times (see, for example, Patent Document 1). It is also said that the read disturb substantially depends upon the number of times of readout from a memory cell. Further, it is also said that, in a multi-value storage device in which 2-bit or more information can be stored in one memory cell, the influence of the read disturb increases because intervals of thresholds for identifying values of stored data are narrow. Therefore, the phenomenon called read disturb is a serious problem for a storage device.
[Patent Document 1] Japanese Patent Document Laid-Open No H10-228783
[Non-Patent Document 1] David A. Patterson and John L. Hennessy, “Computer Organization and Design: The Hardware/Software Interface”, Morgan Kaufman Pub, Aug. 31, 2004